At times it is desired to delay signals, such as binary logic signals, for timing considerations, such as race conditions caused by high speed circuits or paths, skewing of off-chip driver switching to reduce power bus noise, or other such reasons.
Circuits for producing signal delay are well known in the prior art. One known type of signal delay circuit is the basic resistor-capacitor or RC circuit. This type of delay circuit is disclosed in, e.g., U.S. Pat. No. 4,430,587, filed Jan. 13, 1982, entitled "MOS FIXED DELAY CIRCUIT", and U.S. Pat. No. 4,516,312, filed Feb. 10, 1982, entitled "METHOD FOR CONSTRUCTING DELAY CIRCUITS IN A MASTER SLICE IC". Another known type of delay circuit is implemented by an inverter or a series of inverters as disclosed in, e.g., U.S. Pat. No. 4,476,401, filed Jan. 31, 1983, entitled "WRITE STROBE GENERATOR FOR CLOCK SYNCHRONIZED MEMORY", and U.S. Pat. No. 4,700,089, filed Aug. 20, 1985, entitled "DELAY CIRCUIT FOR GATE-ARRAY LSI". A further known type of delay circuit is disclosed in U.S. Pat. No. 4,388,538, filed Sept. 29, 1980, entitled "DELAY SIGNAL GENERATING CIRCUIT", which is implemented in N-channel field effect transistor or NMOS technology and which uses a bootstrap operation and depletion devices. Although not designed as a signal delay circuit, U.S. Pat. No. 4,511,814, filed Nov. 29, 1982, entitled "SEMICONDUCTOR ANALOG SWITCH CIRCUIT WITH COMPENSATION MEANS TO MINIMIZE OFFSET OF CIRCUIT VOLTAGE", discloses a circuit having a pass gate or, more particularly, parallelly connected CMOS transistors, through which signals pass from an input terminal to an output terminal.